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HY29LV400
4 Mbit (512K x 8/256K x 16) Low Voltage Flash Memory
KEY FEATURES
n Single Power Supply Operation
- Read, program and erase operations from 2.7 to 3.6 volts - Ideal for battery-powered applications High Performance - 70 and 90 ns access time versions for full voltage range operation - 55 ns access time version for operation from 3.0 to 3.6 volts Ultra-low Power Consumption (Typical Values) - Automatic sleep mode current: 0.2 A - Standby mode current: 0.2 A - Read current: 7 mA (at 5 Mhz) - Program/erase current: 15 mA Flexible Sector Architecture: - One 16 KB, two 8 KB, one 32 KB and seven 64 KB sectors in byte mode - One 8 KW, two 4 KW, one 16 KW and seven 32 KW sectors in word mode - Top or bottom boot block configurations available Sector Protection - Allows locking of a sector or sectors to prevent program or erase operations within that sector - Sectors lockable in-system or via programming equipment - Temporary Sector Unprotect allows changes in locked sectors (requires high voltage on RESET# pin) Fast Program and Erase Times - Sector erase time: 0.5 sec typical for each sector - Chip erase time: 5 sec typical - Byte program time: 9 s typical - Word program time: 11 s typical Unlock Bypass Program Command - Reduces programming time when issuing multiple program command sequences Automatic Erase Algorithm Preprograms and Erases Any Combination of Sectors or the Entire Chip Automatic Program Algorithm Writes and Verifies Data at Specified Addresses
n Minimum 100,000 Write Cycles per Sector n Compatible With JEDEC standards
- Pinout and software compatible with single-power supply Flash devices - Superior inadvertent write protection Data# Polling and Toggle Bits - Provide software confirmation of completion of program and erase operations Ready/Busy# Pin - Provides hardware confirmation of completion of program and erase operations Erase Suspend/Erase Resume - Suspends an erase operation to allow reading data from, or programming data to, a sector that is not being erased - Erase Resume can then be invoked to complete suspended erasure Hardware Reset Pin (RESET#) Resets the Device to Reading Array Data Space Efficient Packaging - 48-pin TSOP and 48-ball FBGA packages
n
n
n
n
n
n
n n
n
LOGIC DIAGRAM
18 A[17:0] DQ[7:0] 7 CE# OE# WE# RESET# BYTE# DQ[14:8] DQ[15]/A[-1] RY/BY# 8
n
n n n
Preliminary Revision 1.0, November 2001
HY29LV400
GENERAL DESCRIPTION The HY29LV400 is a 4 Mbit, 3 volt-only, CMOS Flash memory organized as 524,288 (512K) bytes or 262,144 (256K) words that is available in 48pin TSOP and 48-ball FBGA packages. Wordwide data (x16) appears on DQ[15:0] and bytewide (x8) data appears on DQ[7:0]. The HY29LV400 can be programmed and erased in-system with a single 3 volt VCC supply. Internally generated and regulated voltages are provided for program and erase operations, so that the device does not require a higher voltage VPP power supply to perform those functions. The device can also be programmed in standard EPROM programmers. Access times as low as 70 ns over the full operating voltage range of 2.7 - 3.6 volts are offered for timing compatibility with the zero wait state requirements of high speed microprocessors. A 55 ns version operating from 3.0 to 3.6 volts is also available. To eliminate bus contention, the HY29LV400 has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device is compatible with the JEDEC singlepower-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. They are then routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a byte/word at a time by executing the four-cycle Program Command write sequence. This initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Faster programming times can be achieved by placing the HY29LV400 in the Unlock Bypass mode, which requires only two write cycles to program data instead of four. The HY29LV400's sector erase architecture allows any number of array sectors to be erased and reprogrammed without affecting the data contents of other sectors. Device erasure is initiated by executing the Erase Command sequence. This initiates an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. As during programming cycles, the device automatically times the erase pulse widths and verifies proper cell margin. Hardware Sector Protection optionally disables both program and erase operations in any combination of the sectors of the memory array, while Temporary Sector Unprotect allows in-system erasure and code changes in previously protected sectors. Erase Suspend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device is fully erased when shipped from the factory. Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (toggle) status bits. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. After a program or erase cycle has been completed, or after assertion of the RESET# pin (which terminates any operation in progress), the device is ready to read data or to accept another command. Reading data out of the device is similar to reading from other Flash or EPROM devices. Two power-saving features are embodied in the HY29LV400. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The host can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.
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Rev. 1.0/Nov. 01
HY29LV400
BLOCK DIAGRAM
DQ[15:0]
A[17:0, 1]
STATE CONTROL
DQ[15:0] WE# CE# OE# BYTE# RESET# RY/BY# PROGRAM VOLTAGE GENERATOR COMMAND REGISTER
ERASE VOLTAGE GENERATOR AND SECTOR SWITCHES I/O CONTROL
I/O BUFFERS
DATA LATCH
ADDRESS LATCH
Y-DECODER
Y-GATING
V C C DETECTOR
TIMER
A[17:0, -1]
X-DECODER
4 Mb FLASH MEMORY ARRAY (11 Sectors)
SIGNAL DESCRIPTIONS
Name A[17:0] DQ[15]/A[-1], DQ[14:0] BYTE# C E# Type Inputs Description Address, active High. These 18 inputs, combined with the DQ[15]/A[-1] input in Byte mode, select one location within the array for read or write operations. Data Bus, active High. These pins provide an 8- or 16-bit data path for read Inputs/Outputs and write operations. In Byte mode, DQ[15]/A[-1] is used as the LSB of the 19-bit Tri-state byte address input. DQ[14:8] are unused and remain tri-stated in Byte mode. Byte Mode, active Low. Low selects Byte mode, High selects Word mode. Input Input Chip Enable, active Low. This input must be asserted to read data from or wri te data to the HY29LV400. When Hi gh, the data bus i s tri -stated and the device is placed in the Standby mode. Output Enable, active Low . Asserted for read operations and negated for write operations. BYTE# determines whether a byte or a word is read during the read operation. W r ite E n a b le , a c tiv e L o w. C o ntro ls wri ti ng o f c o m m a nd s o r c o m m a nd sequences in order to program data or erase sectors of the memory array. A write operation takes place when WE# is asserted while CE# is Low and OE# is High. Hardw are Reset, active Low. Provides a hardware method of resetting the HY29LV400 to the read array state. When the device is reset, it immediately terminates any operation in progress. While RESET# is asserted, the device will be in the Standby mode. R e a d y /B u s y S ta tu s . Ind i c a te s whe the r a wri te o r e ra s e c o mma nd i s i n progress or has been completed. Remai ns Low whi le the devi ce i s acti vely programming data or erasing, and goes High when it is ready to read array data. 3-volt (nominal) pow er supply. Pow er and signal ground.
OE#
Input
WE#
Input
RESET#
Input
RY/BY# V CC V SS
Output Open Drain ---
Rev. 1.0/Nov. 01
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HY29LV400
PIN CONFIGURATIONS
48-Ball FBGA (6 x 8 mm, Top View, Balls Facing Down)
A6
A[13]
B6
A[12]
C6
A[14]
D6
A[15]
E6
A[16]
F6
BYTE#
G6
DQ[15]/A[-1]
H6
V SS
A5
A[9]
B5
A[8]
C5
A[10]
D5
A[11]
E5
DQ[7]
F5
DQ[14]
G5
DQ[13]
H5
DQ[6]
A4
WE#
B4
RESET#
C4
NC
D4
NC
E4
DQ[5]
F4
DQ[12]
G4
V CC
H4
DQ[4]
A3
RY/BY#
B3
NC
C3
NC
D3
NC
E3
DQ[2]
F3
DQ[10]
G3
DQ[11]
H3
DQ[3]
A2
A[7]
B2
A[17]
C2
A[6]
D2
A[5]
E2
DQ[0]
F2
DQ[8]
G2
DQ[9]
H2
DQ[1]
A1
A[3]
B1
A[4]
C1
A[2]
D1
A[1]
E1
A[0]
F1
CE#
G1
OE#
H1
V SS
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TSOP48
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# V SS CE# A0
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Rev. 1.0/Nov. 01
HY29LV400
CONVENTIONS Unless otherwise noted, a positive logic (active High) convention is assumed throughout this document, whereby the presence at a pin of a higher, more positive voltage (VIH) causes assertion of the signal. A `#' symbol following the signal name, e.g., RESET#, indicates that the signal is asserted in the Low state (VIL). See DC specifications for VIH and VIL values. MEMORY ARRAY ORGANIZATION The 4 Mbit Flash memory array is organized into eleven blocks called sectors (S0, S1, . . . , S10). A sector is the smallest unit that can be erased and that can be protected to prevent accidental or unauthorized erasure. See the `Bus Operations' and `Command Definitions' sections of this document for additional information on these functions. In the HY29LV400, four of the sectors, which comprise the boot block, vary in size from 8 to 32 BUS OPERATIONS Device bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. The command register itself does not occupy any addressable memory location. The contents of the command register serve as inputs to an internal state machine whose outputs control the operation of the device. Table 3 lists the normal bus operations, the inputs and control levels they require, and the resulting outputs. Certain bus operations require a high voltage on one or more device pins. Those are described in Table 4.
Read Operation
Whenever a signal is separated into numbered bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of bits may also be shown collectively, e.g., as DQ[7:0]. The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, . . . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a number expressed in binary notation (X = 0, 1). Kbytes (4 to 16 Kwords), while the remaining seven sectors are uniformly sized at 64 Kbytes (32 Kwords). The boot block can be located at the bottom of the address range (HY29LV400B) or at the top of the address range (HY29LV400T). Tables 1 and 2 define the sector addresses and corresponding address ranges for the top and bottom boot block versions of the HY29LV400.
ware reset to ensure that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data, and the device remains enabled for read accesses until the command register contents are altered. This device features an Erase Suspend mode. While in this mode, the host may read the array data from any sector of memory that is not marked for erasure. If the host reads from an address within an erase-suspended (or erasing) sector, or while the device is performing a byte or word program operation, the device outputs status data instead of array data. After completing an Automatic Program or Automatic Erase algorithm within a sector, that sector automatically returns to the read array data mode. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception noted above. The host must issue a hardware reset or the software reset command to return a sector to the read array data mode if DQ[5] goes high during a program or erase cycle, or to return the device to the read array data mode while it is in the Electronic ID mode.
Data is read from the HY29LV400 by using standard microprocessor read cycles while placing the byte or word address on the device's address inputs. The host system must drive the CE# and OE# pins LOW and drive WE# high for a valid read operation to take place. The BYTE# pin determines whether the device outputs array data in words (DQ[15:0]) or in bytes (DQ[7:0]). The HY29LV400 is automatically set for reading array data after device power-up and after a hard-
Rev. 1.0/Nov. 01
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HY29LV400
Table 1. HY29LV400T (Top Boot Block) Memory Array Organization
Sector S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10 Siz e (KB/KW) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 Sector Address 1 A[17] A[16] A[15] A[14] A[13] A[12] 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X 0 1 1 1 X X X X X X X X 0 0 1 X X X X X X X X 0 1 X Byte Mode Address Range 2, 3 0x00000 - 0x0FFFF 0x10000 - 0x1FFFF 0x20000 - 0x2FFFF 0x30000 - 0x3FFFF 0x40000 - 0x4FFFF 0x50000 - 0x5FFFF 0x60000 - 0x6FFFF 0x70000 - 0x77FFF 0x78000 - 0x79FFF 0x7A000 - 0x7BFFF 0x7C000 - 0x7FFFF Word Mode Address Range 2, 3 0x00000 - 0x07FFF 0x08000 - 0x0FFFF 0x10000 - 0x17FFF 0x18000 - 0x1FFFF 0x20000 - 0x27FFF 0x28000 - 0x2FFFF 0x30000 - 0x37FFF 0x38000 - 0x3BFFF 0x3C000 - 0x3CFFF 0X3D000 - 0x3DFFF 0x3E000 - 0x3FFFF
Notes: 1. `X' indicates don't care. 2. `0xN. . . N' indicates an address in hexadecimal notation. 3. The address range in byte mode is A[17:0, -1]. The address range in word mode is A[17:0].
Table 2. HY29LV400B (Bottom Boot Block) Memory Array Organization
Sector S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10 Siz e (KB/KW) 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Sector Address 1 A[17] A[16] A[15] A[14] A[13] A[12] 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 X X X X X X X 0 1 1 X X X X X X X X X 0 1 X X X X X X X X Byte Mode Address Range 2, 3 0x00000 - 0x03FFF 0x04000 - 0x05FFF 0x06000 - 0x07FFF 0x08000 - 0x0FFFF 0x10000 - 0x1FFFF 0x20000 - 0x2FFFF 0x30000 - 0x3FFFF 0x40000 - 0x4FFFF 0x50000 - 0x5FFFF 0x60000 - 0x6FFFF 0x70000 - 0x7FFFF Word Mode Address Range 2, 3 0x00000 - 0x01FFF 0x02000 - 0x02FFF 0X03000 - 0x03FFF 0x04000 - 0x07FFF 0x08000 - 0x0FFFF 0x10000 - 0x17FFF 0x18000 - 0x1FFFF 0x20000 - 0x27FFF 0x28000 - 0x2FFFF 0x30000 - 0x37FFF 0x38000 - 0x3FFFF
Notes: 1. `X' indicates don't care. 2. `0xN. . . N' indicates an address in hexadecimal notation. 3. The address range in byte mode is A[17:0, -1]. The address range in word mode is A[17:0].
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Rev. 1.0/Nov. 01
HY29LV400
Table 3. HY29LV400 Normal Bus Operations 1
Operation Read Write Output Disable CE# Normal Standby CE# Deep Standby Hardware Reset (Normal Standby) Hardware Reset (Deep Standby) C E# L L L H VCC 0.3V X X OE# L H H X X X X WE# H L H X X X X RESET# Address 2 H H H H VCC 0.3V L VSS 0.3V AIN AIN X X X X X DQ[7: 0] DOUT DIN High-Z High-Z High-Z High-Z High-Z DQ[15: 8] 3 BYTE# = H BYTE# = L DOUT DIN High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
Notes: 1. L = VIL, H = VIH, X = Don't Care (L or H), DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels. 2. Address is A[17:0, -1] in Byte Mode and A[17:0] in Word Mode. 3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).
Table 4. HY29LV400 Bus Operations Requiring High Voltage 1, 2
DQ[15: 8] Operation 3 Sector Protect Sector Unprotect Temporary Sector Unprotect 6 Manufacturer Code D evi ce HY29LV400B C ode HY29LV400T Sector Protection Verification CE# OE# WE# RESET# A[19:12] A[9] A[6] A[1] A[0] L L -L L H H -L L L L -H H VID VID VID H H SA 4 X -X X X X -VID VID L H -L L H H -L L L L -L H DQ[7: 0] DIN/DOUT DIN/DOUT -0xAD 0xBA 0xB9 0x00 = Unprotected 0x01 = Protected BYTE# BYTE# =H = L5 X X -X 0x22 X X -High-Z High-Z
L
L
H
H
SA 4
VID
L
H
L
X
High-Z
Notes: 1. L = VIL, H = VIH, X = Don't Care (L OR H). See DC Characteristics for voltage levels. 2. Address bits not specified are Don't Care. 3. See text and for additional information. 4. SA = Sector Address. See Tables 1 and 2. 5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L). 6. Normal read, write and output disable operations are used in this mode. See Table 3.
Rev. 1.0/Nov. 01
7
HY29LV400
Write Operation Certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the HY29LV400. Writes to the device are performed by placing the byte or word address on the device's address inputs while the data to be written is input on DQ[15:0] (BYTE# = High) or DQ[7:0] (BYTE# = Low). The host system must drive the CE# and WE# pins Low and drive OE# High for a valid write operation to take place. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. The "Device Commands" section of this data sheet provides details on the specific device commands implemented in the HY29LV400. Standby Operation When the system is not reading or writing to the device, it can place the HY29LV400 in the Standby mode. In this mode, current consumption is greatly reduced, and the data bus outputs are placed in the high impedance state, independent of the OE# input. The Standby mode can be invoked using two methods. The device enters the CE# Deep Standby mode when the CE# and RESET# pins are both held at VCC 0.3V. Note that this is a more restricted voltage range than VIH . If both CE# and RESET# are held at VIH, but not within VCC 0.3V, the device will be in the CE# Normal Standby mode, but the standby current will be greater. The device enters the RESET# Deep Standby mode when the RESET# pin is held at VSS 0.3V. If RESET# is held at VIL but not within VSS 0.3V, the device will be in the RESET# Normal Standby mode, but the standby current will be greater. See Reset Operation for additional information. The device requires standard access time (tCE) for read access when the device is in either of the standby modes, before it is ready to read data.
Note: If the device is deselected during an erase or programming operation, it continues to draw active current until the operation is completed.
entered when addresses remain stable for tACC + 30 ns (typical) and is independent of the state of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system.
NOTE: Sleep mode is entered only when the device is in Read mode. It is not entered if the device is executing an automatic algorithm, if it is in Erase Suspend mode, or during receipt of a command sequence.
Output Disable Operation When the OE# input is at VIH, output data from the device is disabled and the data bus pins are placed in the high impedance state. Reset Operation The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for the minimum specified period, the device immediately terminates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. If an operation was interrupted by the assertion of RESET#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. Current is reduced for the duration of the RESET# pulse as described in the Standby Operation section above. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains Low (busy) until the internal reset operation is complete, which requires a time of tREADY (during Automatic Algorithms). The system can thus monitor RY/BY# to determine when the reset operation completes, and can perform a read or write operation tRB after RY/BY# goes High. If RESET# is asserted when a program or erase operation is not executing (RY/ BY# pin is High), the reset operation is completed within a time of tRP. In this case, the host can perform a read or write operation tRH after the RESET# pin returns High . The RESET# pin may be tied to the system reset signal. Thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the Flash memory.
Rev. 1.0/Nov. 01
Sleep Mode The sleep mode automatically minimizes device power consumption. This mode is automatically
8
HY29LV400
Sector Protect Operation The hardware sector protection feature disables both program and erase operations in any sector or combination of sectors. This function can be implemented either in-system or by using programming equipment. The Sector Protect procedure requires VID on the RESET# pin and uses standard microprocessor bus cycle timing to implement sector protection. The flow chart in Figure 1 illustrates the algorithm. The HY29LV400 is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See the Electronic ID Mode section for details. Sector Unprotect Operation The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. This function can be implemented either in-system or by using programming equipment. Note that to unprotect any sector, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Also, the unprotect procedure will cause all sectors to become unprotected, thus, sectors that require protection must be protected again after the unprotect procedure is run. The Sector Unprotect procedure requires VID on the RESET# pin and uses standard microprocessor bus cycle timing to implement sector unprotection. The flow chart in Figure 2 illustrates the algorithm. Temporary Sector Unprotect Operation This feature allows temporary unprotection of previously protected sectors to allow changing the data in-system. Sector Unprotect mode is activated by setting the RESET# pin to VID. While in this mode, formerly protected sectors can be programmed or erased by invoking the appropriate commands (see Device Commands section). Once VID is removed from RESET#, all the previously protected sectors are protected again. Figure 3 illustrates the algorithm. Electronic ID Operation (High Voltage Method) The Electronic ID mode provides manufacturer and device identification and sector protection verification through codes output on DQ[15:0]. This mode is intended primarily for programming equipment to automatically match a device to be pro-
START Wait 150 us R E S E T # = V IH R E S E T # = V ID Write 0x40 to Address Write Reset Command Wait 1 us Read from Address SECTOR PROTECT COMPLETE Data = 0x01? TRYCNT = 1 YES Set Address: A[17:12] = Sector to Protect A[6] = 0, A[1] = 1, A[0] = 0 Protect Another Sector? Write 0x60 to Address YES NO NO Increment TRYCNT DEVICE FAILURE NO TRYCNT = 25? YES
Write 0x60 to device
Figure 1. Sector Protect Algorithm
Rev. 1.0/Nov. 01
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HY29LV400
START (Note: All sectors must be protected prior to unprotecting any sector)
Set Address: A[17:12] = Sector SNUM A[6] = 1, A]1] = 1, A]0] = 0
R E S E T # = V IH
TRYCNT = 1 SNUM = 0
Write Reset Command Write 0x40 to Address SECTOR UNPROTECT COMPLETE
R E S E T # = V ID
Read from Address
Wait 1 us Data = 0x00? Write 0x60 to device YES Set Address: A[6] = 1, A]1] = 1, A]0] = 0 SNUM = 10? Write 0x60 to Address Wait 15 ms NO SNUM = SNUM + 1 YES NO Increment TRYCNT DEVICE FAILURE NO TRYCNT = 1000? YES
Figure 2. Sector Unprotect Algorithm
START
grammed with its corresponding programming algorithm. Two methods are provided for accessing the Electronic ID data. The first requires VID on address pin A[9], with additional requirements for obtaining specific data items listed in Table 4. The Electronic ID data can also be obtained by the host through specific commands issued via the command register, as described in the `Device Commands' section of this data sheet. While in the high-voltage Electronic ID mode, the system may read at specific addresses to obtain certain device identification and status information: n A read cycle at address 0xXXX00 retrieves the manufacturer code. n A read cycle at address 0xXXX01 in Word mode or 0xXXX02 in Byte mode returns the device code. n A read cycle containing a sector address (SA) in A[17:12] and the address 0x02 in Word mode or 0x04 in Byte mode, returns 0x01 if that sector is protected, or 0x00 if it is unprotected.
R E S E T # = V ID (All protected sectors become unprotected)
Perform Program or Erase Operations
R E S E T # = V IH (All previously protected sectors return to protected state)
TEMPORARY SECTOR UNPROTECT COMPLETE
Figure 3. Temporary Sector Unprotect Algorithm
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Rev. 1.0/Nov. 01
HY29LV400
DEVICE COMMANDS Device operations are initiated by writing designated address and data command sequences into the device. Addresses are latched on the falling edge of WE# or CE#, whichever happens later. Data is latched on the rising edge of WE# or CE#, whichever happens first. A command sequence is composed of one, two or three of the following sub-segments: an unlock cycle, a command cycle and a data cycle. Table 5 summarizes the composition of the valid command sequences implemented in the HY29LV400, and these sequences are fully described in Table 6 and in the sections that follow. Writing incorrect address and data values or writing them in the improper sequence resets the HY29LV400 to the Read mode. Reading Data The device automatically enters the Read mode after device power-up, after the RESET# input is asserted and upon the completion of certain commands. Commands are not required to retrieve data in this mode. See Read Operation section for additional information. Reset Command Writing the Reset command resets the sectors to the Read or Erase-Suspend mode. Address bits are don't cares for this command. As described above, a Reset command is not normally required to begin reading array data. However, a Reset command must be issued in order to read array data in the following cases: n If the device is in the Electronic ID mode, a Reset command must be written to return to the Read mode. If the device was in the Erase Suspend mode when the device entered the Electronic ID mode, writing the Reset command returns the device to the Erase Suspend mode.
Note: When in the Electronic ID bus operation mode, the device returns to the Read mode when VID is removed from the A[9] pin. The Reset command is not required in this case.
Table 5. Composition of Command Sequences
Command S eq u en ce Reset Read Byte/Word Program Unlock Bypass Unlock Bypass Reset Unlock Bypass Byte/Word Program Chip Erase Sector Erase Erase Suspend Erase Resume Electronic ID Number of Bus Cycles Unlock Command 0 0 2 2 0 0 4 4 0 0 2 1 0 1 1 1 1 1 1 1 1 1 Data 0 Note 1 1 0 1 1 1 1 (Note 2) 0 0 Note 3
Notes: 1. Any number of Flash array read cycles are permitted. 2. Additional data cycles may follow. See text. 3. Any number of Electronic ID read cycles are permitted.
the Read mode (or to the Erase Suspend mode if the device was in Erase Suspend when the Program command was issued). The Reset command may also be used to abort certain command sequences: n In a Sector Erase or Chip Erase command sequence, the Reset command may be written at any time before erasing actually begins, including, for the Sector Erase command, between the cycles that specify the sectors to be erased (see Sector Erase command description). This aborts the command and resets the device to the Read mode. Once erasure begins, however, the device ignores the Reset command until the operation is complete. n In a Program command sequence, the Reset command may be written between the sequence cycles before programming actually begins. This aborts the command and resets the device to the Read mode, or to the Erase Suspend mode if the Program command sequence is written while the device is in the Erase Suspend mode. Once programming begins, however, the device ignores the Reset command until the operation is complete.
11
n If DQ[5] (Exceeded Time Limit) goes High during a program or erase operation, a Reset command must be invoked to return the sectors to
Rev. 1.0/Nov. 01
HY29LV400
Electronic ID 6
12
Bus Cycles 1, 2, 3 First Write Cycles Add Data Add Data Add Data Add Data Add Data Add
0 1 Word Byte Word Byte 2 Word Byte Word Byte Word Byte 1 1 Word Byte Word Byte Word Byte 3 AAA AA 555 555 2A A 3 AAA 555 AA 55 55 555 2A A 3 AAA 555 AA 55 555 2A A 555 AAA 555 AAA 555 AAA XXX 30 90 90 90 X 00 X 01 X 02 AD 22B9 (Top Boot), 22BA (Bottom Boot) B9 (Top Boot), BA (Bottom Boot) (SA)X02 00 = Unprotected Sector (SA)X04 01 = Protected Sector XXX B0 6 AAA 555 AAA AA 55 80 555 2A A 555 6 AAA 555 AAA AA 55 80 555 2A A 555 555 AAA 555 AAA 2 XXX A0 PA PD AA AA 2A A 555 2A A 555 55 55 555 AAA SA 10 30 XXX 90 XXX 00 3 AAA 555 AAA AA 55 555 2A A 555 4 AAA 555 AAA AA 55 A0 PA PD 555 2A A 555 XXX F0 RA RD
Table 6. HY29LV400 Command Sequences
Command Sequence
S eco n d
Third
Fourth
Fifth
Sixth Data
Read
Reset 7
Normal Program
Unlock Bypass
20
Unlock Bypass Reset
Unlock Bypass Program 8
Chip Erase
Sector Erase
Erase Suspend 4
Erase Resume
5
Manufacturer Code
Device Code
Sector Protect Verify
Legend: X = Don't Care RA = Memory address of data to be read RD = Data read from location RA during the read operation
PA = Address of the data to be programmed PD = Data to be programmed at address PA SA = Sector address of sector to be erased or verified (see Note 3 and Tables 1 and 2).
Notes: See next page for notes.
Rev. 1.0/Nov. 01
HY29LV400
Notes for Table 6: 1. All values are in hexadecimal. DQ[15:8] are don't care for unlock and command cycles. 2. All bus cycles are write operations unless otherwise noted. 3. Address is A[10:0] in Word mode and A[10:0, -1] in Byte mode. A[17:11] are don't care except as follows: * For RA and PA, A[17:11] are the upper address bits of the byte to be read or programmed. * For the sixth cycle of Sector Erase, SA = A[17:12] are the sector address of the sector to be erased. * For the fourth cycle of Sector Protect Verify, SA = A[17:12] are the sector address of the sector to be verified. 4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in nonerasing sectors, or enter the Electronic ID mode, while in the Erase Suspend mode. 5. The Erase Resume command is valid only during the Erase Suspend mode. 6. The fourth bus cycle is a read cycle. 7. The command is required only to return to the Read mode when the device is in the Electronic ID command mode. It must also be issued to return to read mode if DQ[5] goes High during a program or erase operation. It is not required for normal read operations. 8. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
n The Reset command may be written between the cycles in an Electronic ID command sequence to abort that command. As described above, once in the Electronic ID mode, the Reset command must be written to return to the array Read mode. Program Command The system programs the device a word or byte at a time by issuing the appropriate four-cycle program command sequence as shown in Table 6. The sequence begins by writing two unlock cycles, followed by the program setup command and, lastly, the program address and data. This initiates the Automatic Program algorithm which automatically provides internally generated program pulses and verifies the programmed cell margin. The host is not required to provide further controls or timings during this operation. When the Automatic Program algorithm is complete, the device returns to the array Read mode (or to the Erase Suspend mode if the device was in Erase Suspend when the Program command was issued). Several methods are provided to allow the host to determine the status of the programming operation, as described in the Write Operation Status section. Commands written to the device during execution of the Automatic Program algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. To ensure data integrity, the aborted Program command sequence should be reinitiated once the reset operation is complete. Programming is allowed in any sequence. Only erase operations can convert a stored "0" to a "1". Thus, a bit cannot be programmed from a "0" back
Rev. 1.0/Nov. 01
to a "1". Attempting to do so may halt the operation and set DQ[5] to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Figure 4 illustrates the programming procedure. Unlock Bypass/Bypass Program/Bypass Reset Commands Unlock bypass provides a faster method for the host system to program the device. As shown in Table 6, the Unlock Bypass command sequence consists of two unlock write cycles followed by a third write cycle containing the Unlock Bypass command, 0x20. In the Unlock Bypass mode, a two-cycle Unlock Bypass Program command sequence is used instead of the standard four-cycle Program sequence to invoke a programming operation. The first cycle in this sequence contains the Unlock Bypass Program command, 0xA0, and the second cycle specifies the program address and data, thus eliminating the initial two unlock cycles required in the standard Program command sequence Additional data is programmed in the same manner. During the Unlock Bypass mode, only the Unlock Bypass program and Unlock Bypass Reset commands are valid. To exit the Unlock Bypass mode, the host must issue the two-cycle Unlock Bypass Reset command sequence shown in Table 6. The device then returns to the array Read mode. Chip Erase Command The Chip Erase command sequence consists of two unlock cycles, followed by a set-up command, two additional unlock cycles and then the Chip Erase command. This sequence invokes the Au13
HY29LV400
START Check Programming Status (See Write Operation Status Section) Enable Fast Programming? DQ[5] Error Exit
NO
Programming Verified
YES Issue UNLOCK BYPASS Command
NO
Last Word/Byte Done?
YES Setup Next Address/Data for Program Operation
NO
Unlock Bypass Mode?
NO
Unlock Bypass Mode?
YES Issue UNLOCK BYPASS RESET Command
Issue NORMAL PROGRAM Command
YES Issue UNLOCK BYPASS PROGRAM Command PROGRAMMING COMPLETE GO TO ERROR RECOVERY PROCEDURE
Figure 4. Normal and Unlock Bypass Programming Procedures tomatic Erase algorithm that automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The host system is not required to provide any controls or timings during these operations. Commands written to the device during execution of the Automatic Erase algorithm are ignored. Note that a hardware reset immediately terminates the chip erase operation. To ensure data integrity, the aborted Chip Erase command sequence should be reissued once the reset operation is complete.
START
When the Automatic Erase algorithm is complete, the device returns to the array Read mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section. Figure 5 illustrates the chip erase procedure. Sector Erase Command The Sector Erase command sequence consists of two unlock cycles, followed by the Erase command, two additional unlock cycles and then the sector erase data cycle, which specifies the sector to be erased. As described later in this section, multiple sectors can be specified for erasure with a single command sequence. During sector erase, all specified sectors are erased sequentially. The data in sectors not specified for erasure, as well as the data in any protected sectors, even if specified for erasure, is not affected by the sector erase operation. The Sector Erase command sequence starts the Automatic Erase algorithm, which preprograms and verifies the specified unprotected sectors for an all zero data pattern prior to electrical erase. The device then provides the required number of
Rev. 1.0/Nov. 01
Issue CHIP ERASE Command Sequence
Check Erase Status (See Write Operation Status Section) Normal Exit
DQ[5] Error Exit
CHIP ERASE COMPLETE
GO TO ERROR RECOVERY
Figure 5. Chip Erase Procedure
14
HY29LV400
internally generated erase pulses and verifies cell erasure within the proper cell margins. The host system is not required to provide any controls or timings during these operations. After the sector erase data cycle (the sixth bus cycle) of the command sequence is issued, a sector erase time-out of 50 s (min), measured from the rising edge of the final WE# pulse in that bus cycle, begins. During this time-out window, an additional sector erase data cycle, specifying the sector address of another sector to be erased, may be written into an internal sector erase buffer. This buffer may be loaded in any sequence, and the number of sectors specified may be from one sector to all sectors. The only restriction is that the time between these additional data cycles must be less than 50 s, otherwise erasure may begin before the last data cycle is accepted. To ensure that all data cycles are accepted, it is recommended that host processor interrupts be disabled during the time that the additional cycles are being issued and then be re-enabled afterwards. If all sectors specified for erasing are protected, the device returns to reading array data after approximately 100 s. If at least one specified sector is not protected, the erase operation erases the unprotected sectors, and ignores the command for the sectors that are protected. The system can monitor DQ[3] to determine if the 50 s sector erase time-out has expired, as described in the Write Operation Status section. If the time between additional sector erase data cycles can be insured to be less than the timeout, the system need not monitor DQ[3]. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must then rewrite the command sequence, including any additional sector erase data cycles. Once the sector erase operation itself has begun, only the Erase Suspend command is valid. All other commands are ignored. As for the Chip Erase command, note that a hardware reset immediately terminates the sector erase operation. To ensure data integrity, the aborted Sector Erase command sequence should be reissued once the reset operation is complete. When the Automatic Erase algorithm terminates, the device returns to the array Read mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section.
START Check Erase Status (See Write Operation Status Section) Normal Exit Write First Five Cycles of SECTOR ERASE Command Sequence ERASE COMPLETE Setup First (or Next) Sector Address for Erase Operation GO TO ERROR RECOVERY DQ[5] Error Exit
Write Last Cycle (SA/0x30) of SECTOR ERASE Command Sequence NO Sector Erase Time-out (DQ[3]) Expired?
Sectors which require erasure but which were not specified in this erase cycle must be erased later using a new command sequence
Erase An Additional Sector?
YES
YES
NO
Figure 6. Sector Erase Procedure
Rev. 1.0/Nov. 01
15
HY29LV400
Figure 6 illustrates the Sector Erase procedure. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation to read data from, or program data in, any sector not being erased. The command causes the erase operation to be suspended in all sectors specified for erasure. This command is valid only during the sector erase operation, including during the 50 s time-out period at the end of the command sequence, and is ignored if it is issued during chip erase or programming operations. The HY29LV400 requires a maximum of 20 s to suspend the erase operation if the Erase Suspend command is issued during sector erasure. However, if the command is written during the timeout, the time-out is terminated and the erase operation is suspended immediately. Once the erase operation has been suspended, the system can read array data from or program data to any sector not specified for erasure. Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ[7:0]. The host can use DQ[7], or DQ[6] and DQ[2] together, to determine if a sector is actively erasing or is erasesuspended. See the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the host can initiate another programming operation (or read operation) within non-suspended sectors. The host can determine the status of a program operation during the Erase-Suspended state just as in the standard programming operation. The host may also write the Electronic ID command sequence when the device is in the Erase Suspend mode. The device allows reading Electronic ID codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the Electronic ID mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Electronic ID Mode section for more information. The system must write the Erase Resume command to exit the Erase Suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. Electronic ID Command The Electronic ID mode provides manufacturer and device identification and sector protection verification through identifier codes output on DQ[7:0]. This mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. Two methods are provided for accessing the Electronic ID data. The first requires VID on address pin A[9], as described previously in the Device Operations section. The Electronic ID data can also be obtained by the host by invoking the Electronic ID command, as shown in Table 6. This method does not require VID. The Electronic ID command sequence may be issued while the device is in the Read mode or in the Erase Suspend Read mode, that is, except while programming or erasing. The Electronic ID command sequence is initiated by writing two unlock cycles, followed by the Electronic ID command. The device then enters the Electronic ID mode, and the system may read at any address any number of times, without initiating another command sequence. n A read cycle at address 0xXXX00 retrieves the manufacturer code. n A read cycle at address 0xXXX01 in Word mode or 0xXXX02 in Byte mode returns the device code. n A read cycle containing a sector address (SA) in A[17:12] and the address 0x02 in A[7:0] in Word mode (or 0x04 in A[6:0, -1] in Byte mode) returns 0x01 if that sector is protected, or 0x00 if it is unprotected. The system must write the Reset command to exit the Electronic ID mode and return to reading array data.
16
Rev. 1.0/Nov. 01
HY29LV400
Table 7. Write and Erase Operation Status Summary
Mode Operation Programming in progress Normal Programming completed Erase in progress Erase completed
5
DQ[7] Data 0 Data 1 Data
1
DQ[6] Toggle Data Data
4
DQ[5] 0/1 0/1
2
DQ[3] N/A Data 1
3
DQ[2] N/A Data
1
RY/BY# 0 1 0 1 1 1 0 1
DQ[7]#
Data
2
Toggle
4
Toggle Data
4
Data 0 Data 0/1 2 Data
Data N/A Data N/A Data
Read within erase suspended sector Read within non-erase Erase Suspend suspended sector Programming in progress 6 Programming completed
6
No toggle Data Toggle Data
4
Toggle Data N/A Data
DQ[7]# Data
Notes: 1. A valid address is required when reading status information. See text for additional information. 2. DQ[5] status switches to a `1' when a program or erase operation exceeds the maximum timing limit. 3. A `1' during sector erase indicates that the 50 s time-out has expired and active erasure is in progress. DQ[3] is not applicable to the chip erase operation. 4. Equivalent to `No Toggle' because data is obtained in this state. 5. Data (DQ[7:0]) = 0xFF immediately after erasure. 6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).
WRITE OPERATION STATUS The HY29LV400 provides a number of facilities to determine the status of a program or erase operation. These are the RY/BY# (Ready/Busy#) pin and certain bits of a status word which can be read from the device during the programming and erase operations. Table 7 summarizes the status indications and further detail is provided in the subsections which follow. RY/BY# - Ready/Busy# RY/BY# is an open-drain output pin that indicates whether a programming or erase Automatic Algorithm is in progress or has completed. A pull-up resistor to VCC is required for proper operation. RY/ BY# is valid after the rising edge of the final WE# pulse in the corresponding command sequence. If the output is Low (busy), the device is actively erasing or programming, including programming while in the Erase Suspend mode. If the output is High (ready), the device has completed the operation and is ready to read array data in the normal or Erase Suspend modes, or it is in the Standby mode. DQ[7] - Data# Polling The Data# ("Data Bar") Polling bit, DQ[7], indicates to the host system whether an Automatic AlgoRev. 1.0/Nov. 01
rithm is in progress or completed, or whether the device is in Erase Suspend mode. Data# Polling is valid after the rising edge of the final WE# pulse in the Program or Erase command sequence. The system must do a read at the program address to obtain valid programming status information on this bit. While a programming operation is in progress, the device outputs the complement of the value programmed to DQ[7]. When the programming operation is complete, the device outputs the value programmed to DQ[7]. If a program operation is attempted within a protected sector, Data# Polling on DQ[7] is active for approximately 1 s, then the device returns to reading array data. The host must read at an address within any nonprotected sector specified for erasure to obtain valid erase status information on DQ[7]. During an erase operation, Data# Polling produces a "0" on DQ[7]. When the erase operation is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ[7]. If all sectors selected for erasing are protected, Data# Polling on DQ[7] is active for approximately 100 s, then the device returns to reading array data. If at least one selected sector is not protected, the erase operation erases the unprotected sectors,
17
HY29LV400
and ignores the command for the specified sectors that are protected. When the system detects that DQ[7] has changed from the complement to true data (or "0" to "1" for erase), it should do an additional read cycle to read valid data from DQ[7:0]. This is because DQ[7] may change asynchronously with respect to the other data bits while Output Enable (OE#) is asserted low. Figure 7 illustrates the Data# Polling test algorithm. DQ[6] - Toggle Bit I Toggle Bit I on DQ[6] indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the Program or Erase command sequence, including during the sector erase time-out. The system may use either OE# or CE# to control the read cycles. Successive read cycles at any address during an Automatic Program algorithm operation (including programming while in Erase Suspend mode) cause DQ[6] to toggle. DQ[6] stops toggling when the operation is complete. If a program address falls within a protected sector, DQ[6] toggles for approximately one s after the program command sequence is written, then returns to reading array data. While the Automatic Erase algorithm is operating, successive read cycles at any address cause DQ[6] to toggle. DQ[6] stops toggling when the erase operation is complete or when the device is placed in the Erase Suspend mode. The host may use DQ[2] to determine which sectors are erasing or erase-suspended (see below). After an Erase command sequence is written, if all sectors selected for erasing are protected, DQ[6] toggles for approximately 100 s, then returns to reading array data. If at least one selected sector is not protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. DQ[2] - Toggle Bit II Toggle Bit II, DQ[2], when used with DQ[6], indicates whether a particular sector is actively erasing or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. The device toggles DQ[2] with each OE# or CE# read cycle. DQ[2] toggles when the host reads at addresses within sectors that have been specified for erasure, but cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ[6], by comparison, indicates whether the device is actively erasing or is in Erase Suspend, but cannot distinguish which sectors are specified for erasure. Thus, both status bits are required for sector and mode information. Figure 8 illustrates the operation of Toggle Bits I and II. DQ[5] - Exceeded Timing Limits DQ[5] is set to a `1' when the program or erase time has exceeded a specified internal pulse count
Rev. 1.0/Nov. 01
START
Read DQ[7:0] at Valid Address (Note 1) Test for DQ[7] = 1? for Erase Operation DQ[7] = Data? YES
NO
NO
DQ[5] = 1?
YES Read DQ[7:0] at Valid Address (Note 1) Test for DQ[7] = 1? for Erase Operation DQ[7] = Data? (Note 2) YES
NO PROGRAM/ERASE EXCEEDED TIME ERROR PROGRAM/ERASE COMPLETE
Notes: 1. During programming , the program address. During sector erase , an address within any non-protected sector specified for erasure. During chip erase , an address within any non-protected sector. 2. Recheck DQ[7] since it may change asynchronously to DQ[5].
Figure 7. Data# Polling Test Algorithm
18
HY29LV400
START
DQ[5] = 1? Read DQ[7:0] at Valid Address (Note 1) NO YES Read DQ[7:0] at Valid Address (Note 1) Read DQ[7:0] at Valid Address (Note 1) Read DQ[7:0] Read DQ[7:0]
YES NO (Note 4) DQ[6] Toggled?
NO
DQ[6] Toggled? (Note 2)
NO DQ[2] Toggled?
NO (Note 3) PROGRAM/ERASE COMPLETE
YES PROGRAM/ERASE EXCEEDED TIME ERROR
YES SECTOR BEING READ IS IN ERASE SUSPEND SECTOR BEING READ IS NOT IN ERASE SUSPEND
Notes: 1. During programming, the program address. During sector erase, an address within any sector scheduled for erasure. 2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1. 3. Use this path if testing for Program/Erase status. 4. Use this path to test whether sector is in Erase Suspend mode.
Figure 8. Toggle Bit I and II Test Algorithm limit. This is a failure condition that indicates that the program or erase cycle was not successfully completed. DQ[5] status is valid only while DQ[7] or DQ[6] indicate that the Automatic Algorithm is in progress. The DQ[5] failure condition will also be signaled if the host tries to program a `1' to a location that is previously programmed to `0', since only an erase operation can change a `0' to a `1'. For both of these conditions, the host must issue a Reset command to return the device to the Read mode. DQ[3] - Sector Erase Timer After writing a Sector Erase command sequence, the host may read DQ[3] to determine whether or not an erase operation has begun. When the sector erase time-out expires and the sector erase operation commences, DQ[3] switches from a `0' to a `1'. Refer to the "Sector Erase Command" section for additional information. Note that the sector erase timer does not apply to the Chip Erase command. After the initial Sector Erase command sequence is issued, the system should read the status on DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ[3]. If DQ[3] is a `1', the internally controlled erase cycle has begun and all further sector erase data cycles or commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ[3] is a `0', the device will accept a sector erase data cycle to mark an additional sector for erasure. To ensure that the data cycles have been accepted, the system software should check the status of DQ[3] prior to and following each subsequent sector erase data cycle. If DQ[3] is high on the second status check, the last data cycle might not have been accepted.
Rev. 1.0/Nov. 01
19
HY29LV400
HARDWARE DATA PROTECTION The HY29LV400 provides several methods of protection to prevent accidental erasure or programming which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. These methods are described in the sections that follow. Command Sequences Commands that may alter array data require a sequence of cycles as described in Table 6. This provides data protection against inadvertent writes. Low VCC Write Inhibit To protect data during VCC power-up and powerdown, the device does not accept write cycles when VCC is less than VLKO (typically 2.4 volts). The command register and all internal program/erase circuits are disabled, and the device resets to the Read mode. Writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by asserting any one of the following conditions: OE# = VIL , CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the Read mode on powerup. Sector Protection Additional data protection is provided by the HY29LV400's sector protect feature, described previously, which can be used to protect sensitive areas of the Flash array from accidental or unauthorized attempts to alter the data.
20
Rev. 1.0/Nov. 01
HY29LV400
ABSOLUTE MAXIMUM RATINGS 4
Symbol TSTG TBIAS VIN2 IOS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage on Pin with Respect to VSS : VC C 1 A[9], OE#, RESET# 2 All Other Pins 1 Output Short Circuit Current 3 Value -65 to +150 -65 to +125 -0.5 to +4.0 -0.5 to +12.5 -0.5 to VCC +0.5 200 Unit C C V V V mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10. 2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET# may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A[9] is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS 1
Symbol TA Parameter Ambient Operating Temperature: Commercial Temperature Devices Industrial Temperature Devices Operating Supply Voltage: -55 Version Other Versions Value 0 to +70 -40 to +85 +3.0 to +3.6 +2.7 to +3.6 Unit C C V V
V CC
Notes: 1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.
20 ns 0.8 V - 0.5 V
20 ns V C C + 2.0 V
20 ns
V C C + 0.5 V - 2.0 V 20 ns 2.0 V 20 ns 20 ns
Figure 9. Maximum Undershoot Waveform
Figure 10. Maximum Overshoot Waveform
Rev. 1.0/Nov. 01
21
HY29LV400
DC CHARACTERISTICS
Parameter Description ILI Input Load Current A[9] Input Load Current ILIT Output Leakage Current ILO Test Setup 2 VIN = VSS to VCC A[9] = 12.5 V VOUT = VSS to VCC CE# = VIL, 5 MHz OE# = VIH, 1 MHz Byte Mode CE# = VIL, 5 MHz OE# = VIH, 1 MHz Word Mode CE# = VIL, OE# = VIH CE# = VCC 0.3 V, RESET# = VCC 0.3 V RESET# = VSS 0.3 V VIH = VCC 0.3 V, VIL = VSS 0.3 V CE# = RESET# = VIH RESET# = VIL -0.5 0.7 x VCC VCC = 3.3V VCC = VCC Min, IOL = 4.0 mA VCC = VCC Min, IOH = -2.0 mA VCC = VCC Min, IOH = -100 A 11.5 Min Typ Max 1.0 35 1.0 12 4 12 4 30 5 5 5 1 1 0.8 VCC + 0.3 12.5 0.45 0.85 x VCC VCC - 0.4 2.3 2.5 Unit A A A mA mA mA mA mA A A A mA mA V V V V V V V
7 2 7 2 15 0.2 0.2 0.2
ICC1
VCC Active Read Current 1
ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VID VOL VOH1
VCC Active Write Current VCC CE# Controlled Deep Standby Current VCC RESET# Controlled Deep Standby Current Automatic Sleep Mode Current 5, VCC CE# Controlled Normal Standby Current 2 VCC RESET# Controlled Normal Standby Current 2 Input Low Voltage Input High Voltage Voltage for Electronic ID and Temporary Sector Unprotect Output Low Voltage
3, 4
Output High Voltage VOH2 V LK O Low VCC Lockout Voltage4
Notes: 1. The ICC current is listed is typically less than 2 mA/MHz with OE# at VIH. Typical VCC is 3.0 V. 2. All specifications are tested with VCC = VCC Max unless otherwise noted. 3. ICC active while the Automatic Erase or Automatic Program algorithm is in progress. 4. Not 100% tested. 5. Automatic sleep mode is enabled when addresses remain stable for tACC + 30 ns (typical).
22
Rev. 1.0/Nov. 01
HY29LV400
DC CHARACTERISTICS Zero Power Flash
20
15 Supply Current in mA
10
5
0 0 500 1000 1500 2000 Time in ns 2500 3000 3500 4000
Note: Addresses are switching at 1 MHz.
Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
8
3.6 V
6 Supply Current in mA
2.7 V
4
2
0 1 2 3 Frequency in MHz Note: T = 25 C. 4 5
Figure 12. Typical ICC1 Current vs. Frequency
Rev. 1.0/Nov. 01
23
HY29LV400
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUT S Steady OUT PUT S
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown Centerline is High Impedance State (High Z)
Does Not Apply
TEST CONDITIONS Table 12. Test Specifications
+ 3.3V
Test Condition
2.7 KOhm
- 55
- 70 - 90 100 5 0.0 3.0 1.5 1.5
Unit
Output Load Output Load Capacitance (CL) Input Rise and Fall Times Input Signal Low Level Input Signal High Level Low Timing Measurement Signal Level High Timing Measurement Signal Level 30
1 TTL Gate pF ns V V V V
DEVICE UNDER TEST CL 6.2 KOhm
All diodes are 1N3064 or equivalent
Figure 13. Test Setup
Note: Timing measurements are made at the reference levels specified above regardless of where the illustrations in the timing diagrams appear to indicate the measurement is made
3.0 V Input 0.0 V 1.5 V Measurement Level 1.5 V Output
Figure 14. Input Waveforms and Measurement Levels
24
Rev. 1.0/Nov. 01
HY29LV400
AC CHARACTERISTICS Read Operations
Parameter JE D E C tAVAV tAVQV tELQV tEHQZ tGLQV tGHQZ Std tRC tACC tCE tDF tOE tDF tOEH tAXQX tOH Description Read Cycle Time 1 Address to Output Delay Chip Enable to Output Delay Chip Enable to Output High Z 1 Output Enable to Output Delay Output Enable to Output High Z 1 Read Output Enable Toggle and Hold Time 1 Data# Polling Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First 1 CE# = VIL OE# = VIL OE# = VIL CE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed Option - 55 55 55 55 25 30 25 -70 70 70 70 25 30 25 0 10 0 - 90 90 90 90 30 35 30 Unit ns ns ns ns ns ns ns ns ns
Notes: 1. Not 100% tested.
tR C Addresses Addresses Stable tA C C CE# tO E OE# tO E H WE# tC E tD F
tO H Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 15. Read Operation Timings
Rev. 1.0/Nov. 01
25
HY29LV400
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JE D E C Std tREADY tREADY tRP tRH tRPD tRB Description RESET# Pin Low (During Automatic Algorithms) to Read or Write 1 RESET# Pin Low (NOT During Automatic Algorithms) to Read or Write 1 RESET# Pulse Width RESET# High Time Before Read 1 RESET# Low to Standby Mode RY/BY# Recovery Time Test Setup Max Max Min Min Max Min Speed Option - 55 - 70 20 500 500 50 20 0 - 90 Unit s ns ns ns s ns
Notes: 1. Not 100% tested.
RY/BY# CE#, OE#
0V
tR H RESET# tR P t Ready
Reset Timings NOT During Automatic Algorithms
RY/BY# CE#, OE# RESET# tR P
t Ready tRB
Reset Timings During Automatic Algorithms Figure 16. RESET# Timings
26
Rev. 1.0/Nov. 01
HY29LV400
AC CHARACTERISTICS Word/Byte Configuration (BYTE#)
Parameter JE D E C Std tELFL tELFH tFLQZ tFHQV Description CE# to BYTE# Switching Low CE# to BYTE# Switching High BYTE# Switching Low to Output High-Z BYTE# Switching High to Output Active Max Max Max Min Speed Option - 55 - 70 5 5 25 70 - 90 Unit ns ns ns ns
25 55
30 90
CE# OE# BYTE# BYTE# switching from word to byte mode DQ[14:0] DQ[15]/A-1 tF L Q Z BYTE# DQ[14:0]
Data Output DQ[7:0] Data Output DQ[14:0]
tELFL
Data Output DQ[14:0] Data Output DQ[7:0]
Output DQ[15]
Address Input A-1
BYTE# switching from byte to word mode
DQ[15]/A-1 tE L F H
Address Input A-1
Data Output DQ[15]
tF H Q V
Figure 17. BYTE# Timings for Read Operations
CE# Falling edge of the last WE# signal WE# t S E T (t A S ) BYTE#
Note: Refer to the Program/Erase Operations table for tAS and tAH specifications.
t H O L D (t A H )
Figure 18. BYTE# Timings for Write Operations
Rev. 1.0/Nov. 01
27
HY29LV400
AC CHARACTERISTICS Program and Erase Operations
Parameter JE D E C tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL Std tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH Description Write Cycle Time 1 Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Byte Mode tWHWH1 tWHWH1 Programming Operation
1, 2, 3
Speed Option - 55 Min Min Min Min Min Min Min Min Min Min Typ Max Typ Max Typ Max Typ Max Typ Max Typ Typ Min Min Min Min 55 35 35 - 70 70 0 45 35 0 0 0 0 35 30 9 300 11 360 4.5 13.5 2.9 8.7 0.5 10 5 1,000,000 100,000 50 0 90 - 90 90 45 45
Unit ns ns ns ns ns ns ns ns ns ns s s s s se c se c se c se c se c se c se c cycles cycles s ns ns
35
35
Word Mode Byte Mode Chip Programming Operation 1, 2, 3, 5 Word Mode tWHWH2 tWHWH3 tWHWH2 Sector Erase Operation 1, 2, 4 tWHWH3 Chip Erase Operation 1, 2, 4 Erase and Program Cycle Endurance 1 tVCS tRB tBUSY VCC Setup Time 1 Recovery Time from RY/BY# WE# High to RY/BY# Delay
Notes: 1. Not 100% tested. 2. Typical program and erase times assume the following conditions: 25 C, VCC = 3.0 volts, 100,000 cycles. In addition, programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 C, VCC = 2.7 volts (3.0 volts for - 55 version), 100,000 cycles. 3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. See Table 6 for further information on command sequences. 4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes are programmed to 0x00 before erasure. 5. The typical chip programming time is considerably less than the maximum chip programming time listed since most bytes/words program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum byte/word program time specified is exceeded. See Write Operation Status section for additional information.
28
Rev. 1.0/Nov. 01
HY29LV400
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tW C Addresses CE# tG H W L OE# WE# tC S tD S 0xA0 tW P 0x555
tA S PA
tA H PA PA
tC H tW P H tD H tW H W H 1 PD tB U S Y Status D OUT tR B
Data
RY/BY# V CC tV C S
Notes: 1. PA = Program Address, PD = Program Data, DOUT is the true data at the program address. 2. Commands shown are for Word mode operation. 3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 19. Program Operation Timings
Rev. 1.0/Nov. 01
29
HY29LV400
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data (last two cycles)
tW C Addresses CE# tG H W L OE# tW P WE# tC S tD S tC H 0x2AA
tA S SA
tA H VA
Address = 0x555 for chip erase
VA
tW P H tD H
Data = 0x10 for chip erase
t W H W H 2 or tW H W H 3 Status D OUT tR B
Data
0x55
0x30 tB U S Y
RY/BY# V CC tV C S
Notes: 1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section), DOUT is the true data at the read address.(0xFF after an erase operation). 2. Commands shown are for Word mode operation. 3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 20. Sector/Chip Erase Operation Timings
30
Rev. 1.0/Nov. 01
HY29LV400
AC CHARACTERISTICS
tR C Addresses tC H CE# tC E OE# tO E H WE# tO E tD F tO H
Complement Complement True Valid Data
VA tA C C
VA
VA
DQ[7] DQ[6:0] tB U S Y RY/BY#
Status Data
Status Data
Data
Valid Data
Notes: 1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section). 2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.
Figure 21. Data# Polling Timings (During Automatic Algorithms)
tR C Addresses tC H CE# tC E OE# tO E H WE# tO E tD F tO H
Valid Status Valid Status (second read) Valid Status (stops toggling) Valid Data
VA tA C C
VA
VA
VA
DQ[6], [2] tB U S Y RY/BY#
(first read)
Notes: 1. VA = Valid Address for reading Toggle Bits (DQ[2], DQ[6]) status data (see Write Operation Status section). 2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.
Figure 22. Toggle Polling Timings (During Automatic Algorithms)
Rev. 1.0/Nov. 01
31
HY29LV400
AC CHARACTERISTICS
Enter Automatic Erase Erase Suspend Erase Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
WE#
DQ[6] DQ[2]
Notes: 1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an erase-suspended sector.
Figure 23. DQ[2] and DQ[6] Operation Sector Protect and Unprotect, Temporary Sector Unprotect
Parameter JE D E C Std tVIDR tRSP tVRES tPROT tUNPR Description VID Transition Time for Temporary Sector Unprotect 1 RESET# Setup Time for Temporary Sector Unprotect RESET# Setup Time for Sector Protect and Unprotect Sector Protect Time Sector Unprotect Time Min Min Min Max Max Speed Option - 55 - 70 500 4 1 150 15 - 90 Unit ns s s s ms
Notes: 1. Not 100% tested.
V ID
RESET#
0 or 3V 0 or 3V
t VIDR
t VIDR
CE#
WE# tR S P RY/BY#
Figure 24. Temporary Sector Unprotect Timings
32
Rev. 1.0/Nov. 01
HY29LV400
AC CHARACTERISTICS
V ID
RESET#
V IH
SA, A[6], A[1], A[0] Data
tV R E S
Don't Care
Valid *
Valid * Verify 0x40 tP R O T
Valid *
Sector Protect/Unprotect 0x60 0x60
Status
CE#
tU N P R
WE#
OE#
Note: For Sector Protect, A[6] = 0, A[1] = 1, A[0] = 0. For Sector Unprotect, A[6] = 1, A[1] = 1, A[0] = 0.
Figure 25. Sector Protect and Unprotect Timings Alternate CE# Controlled Program and Erase Operations 2
Parameter JE D E C tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tBUSY Description Write Cycle Time 1 Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High CE# to RY/BY# Delay Min Min Min Min Min Min Min Min Min Min Min Speed Option - 55 55 45 35 - 70 70 0 45 35 0 0 0 0 35 30 90 - 90 90 45 45 Unit ns ns ns ns ns ns ns ns ns ns ns
35
35
Notes: 1. Not 100% tested. 2. See Program and Erase Operations table for program and erase characteristics.
Rev. 1.0/Nov. 01
33
HY29LV400
AC CHARACTERISTICS
PA for Program SA for Sector Erase 0x555 for Chip Erase
0x555 for Program 0x2AA for Erase
Addresses tW C WE# tG H E L OE# tW S CE# tD S Data
0xA0 for Program 0x55 for Erase PD for Program 0x30 for Sector Erase 0x10 for Chip Erase
VA tA S tA H
tW H tC P tC P H t W H W H 1 or t W H W H 2 or t W H W H 3 tB U S Y Status D OUT
tD H
RY/BY# tR H RESET#
Notes: 1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write Operation Status section), DOUT = array data read at VA. 2. 3. 4. Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle. Word mode addressing shown. RESET# shown only to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence.
Figure 26. Alternate CE# Controlled Write Operation Timings
34
Rev. 1.0/Nov. 01
HY29LV400
Latchup Characteristics
Description Input voltage with respect to VSS on all pins except I/O pins(including A[9], OE# and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Minimum - 1.0 - 1.0 - 100 Maximum 12.5 VCC + 1.0 100 Unit V V mA
Notes: 1. Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
TSOP and PSOP Pin Capacitance
Symbol CIN COUT CIN2 Parameter Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions: TA = 25 C, f = 1.0 MHz.
Data Retention
Parameter Minimum Pattern Data Retention Time Test Conditions 150 C 125 C Minimum 10 20 Unit Years Years
Rev. 1.0/Nov. 01
35
HY29LV400
PACKAGE DRAWINGS Physical Dimensions TSOP48 - 48-pin Thin Small Outline Package (measurements in millimeters)
0.95 1.05 Pin 1 ID
1 48
11.90 12.10
0.50 BSC
24
25
18.30 18.50 19.80 20.20
0.05 0.15
1.20 MAX 0.25MM (0.0098") BSC 0 o 5 0.50 0.70
o
0.08 0.20 0.10 0.21
36
Rev. 1.0/Nov. 01
HY29LV400
PACKAGE DRAWINGS Physical Dimensions FBGA48 - 48-Ball Fine-Pitch Ball Grid Array, 6 x 8 mm (measurements in millimeters)
Note: Unless otherwise specified, tolerance = 0.05
0.10 C 8.00 0.10 A
1.80 0.10
A1 CORNER INDEX AREA
2.10 0.10
C
6.00 0.10
0.10 C B
C
0.10 C
1.10 MAX 0.20 MIN
0.76 TYP
Seating Plane C 0.08 C 5.60 BSC
H 6 5 4
G
F
E
D
C
B
A
0.40 BSC 4.00 BSC
C
3 2 1
0.80 TYP Pin A1 Index Mark
O 0.30 0.05 O 0.15 M C A B O 0.08 M C
0.40 BSC
C
Rev. 1.0/Nov. 01
37
HY29LV400
ORDERING INFORMATION Hynix products are available in several speeds, packages and operating temperature ranges. The ordering part number is formed by combining a number of fields, as indicated below. Refer to the `Valid Combinations' table, which lists the configurations that are planned to be supported in volume. Please contact your local Hynix representative or distributor to confirm current availability of specific configurations and to determine if additional configurations have been released.
HY29LV400 X X X X X SPECIAL INSTRUCTIONS TEMPERATURE RANGE Blank = Commercial ( 0 to +70 C) I = Industrial (-40 to +85 C) SPEED OPTION 55 = 55 ns 70 = 70 ns 90 = 90 ns PACKAGE TYPE T = 48-Pin Thin Small Outline Package (TSOP) F = 48-Ball Fine-Pitch Ball Grid Array (FBGA), 8 x 9 mm BOOT BLOCK LOCATION T = Top Boot Block Option B = Bottom Boot Block Option DEVICE NUMBER HY29LV400 = 4 Megabit (512K x 8/256K x 16) CMOS 3 Volt-Only Sector Erase Flash Memory
VALID COMBINATIONS
P ackag e an d S p eed TSOP Temperature Commercial Industrial 55 n s T-55 T-55I 70 n s T-70 T-70I 90 n s T-90 T-90I 55 n s F-55 F-55I FBGA 70 n s F-70 F-70I 90 n s F-90 F-90I
Note: 1. The complete part number is formed by appending the suffix shown in the table above to the Device Number. For example, the part number for a 90 ns, top boot block, Industrial temperature range device in the TSOP package is HY29LV400TT-90I.
38
Rev. 1.0/Nov. 01
HY29LV400
Rev. 1.0/Nov. 01
39
HY29LV400 Important Notice
(c) 2001 by Hynix Semiconductor America. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Hynix Semiconductor Inc. or Hynix Semiconductor America (collectively "Hynix"). The information in this document is subject to change without notice. Hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. Hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. Devices sold by Hynix are covered by warranty and patent indemnification provisions appearing in Hynix Terms and Conditions of Sale only. Hynix makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Hynix makes no warranty of merchantability or fitness for any purpose. Hynix's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Hynix prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustain life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
Revision Record Rev.
1.0
Date
10/01 Initial release.
Details
Flash Memory Business Unit, Korea Hynix Semiconductor Inc. 891, Daechi-dong Kangnam-gu Seoul, Korea Telephone: +82-2-3459-5980 Fax: +82-2-3459-5988 http://www.hynix.com
40
Flash Memory Business Unit, HQ Hynix Semiconductor Inc. 3101 North First Street San Jose, CA 95134 USA Telephone: (408) 232-8800 Fax: (408) 232-8805 http://www.us.hynix.com
Rev. 1.0/Nov. 01

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